Formal Semantics and Proof Techniques for Optimizing VHDL Models / Najlacnejšie knihy
Formal Semantics and Proof Techniques for Optimizing VHDL Models

Code: 01397588

Formal Semantics and Proof Techniques for Optimizing VHDL Models

by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows ... more

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Book synopsis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Book details

Book category Books in English Computing & information technology Computer programming / software development Programming & scripting languages: general

102.97 €

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