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Book synopsis

The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore).Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board (such a board can be freely obtained from the Xilinx University Program targeting the university professors).The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators.

Book details

Book category Books in English Computing & information technology Computer science Computer architecture & logic design

• Full title: Guide to Computer Processor Architecture
• Subtitle: A RISC-V Approach, with High-Level Synthesis
• Author: Bernard Goossens
• Language: English
• Binding: Paperback
• Number of pages: 468
• EAN: 9783031180224
• ID: 41443051
• Publisher: Springer International Publishing AG
• Weight: 888 g
• Dimensions: 235 × 155 mm
• Date of publishing: 13. January 2023

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