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Book synopsis

The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.§Topics included in the new Second Edition: Discussions on OpenVera and e; Approaches for writing constrainable random stimulus generators; Strategies for making testbenches self-checking; A clear blueprint of a verification process that aims for first time success; Recent advances in functional verification such as coverage-driven verification process; VHDL and Verilog language semantics; The semantics are presented in new verification-oriented languages; Techniques for applying stimulus and monitoring the response of a design; Behavioral modeling using non-synthesizeable constructs and coding style; Updated for Verilog 2001.

Book details

Book category Books in English Computing & information technology Computer programming / software development Programming & scripting languages: general

• Full title: Writing Testbenches: Functional Verification of HDL Models
• Subtitle: Functional Verification of HDL Models
• Author: Janick Bergeron
• Language: English
• Binding: Hardback
• Number of pages: 478
• EAN: 9781402074011
• ISBN: 1402074018
• ID: 01417963
• Publisher: Springer-Verlag New York Inc.
• Weight: 894 g
• Dimensions: 242 × 166 × 35 mm
• Date of publishing: 28. February 2003

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