Code: 16880282
Learn to model for synthesis using VHDL. See the details of how VHDL gets translated into logic gates in this book. Also, see how hardware elements are described in synthesizable VHDL. This book is a must primer for anyone who is ... more
English
75.62 €
RRP: 81.33 €
You save 5.70 €

You get 183 loyalty points
Book synopsis
Learn to model for synthesis using VHDL. See the details of how VHDL gets translated into logic gates in this book. Also, see how hardware elements are described in synthesizable VHDL. This book is a must primer for anyone who is beginning to learn synthes
Book details
75.62 €
English
Collection points Bratislava a 13537 dalších
Copyright ©2008-26 najlacnejsie-knihy.sk All rights reservedPrivacyCookies
27078 collection points
Delivery 2.99 €
02/210 210 99 (8-15.30h)Shopping cart ( Empty )
You are here: