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Opis

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Szczegóły książki

• Pełny tytuł: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
• Autor: Zheng Wang, Anupam Chattopadhyay
• Język: Angielski
• Oprawa: Miękka
• Liczba stron: 197
• EAN: 9789811093210
• ID: 20095107
• Wydawca: Springer Verlag, Singapore
• Waga: 3401 g
• Wymiary: 235 × 155 × 13 mm
• Data wydania: 12. May 2018

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