Instruction Level Parallelism / Najlacnejšie knihy
Instruction Level Parallelism

Kód: 06989549

Instruction Level Parallelism

Autor Rajendra Kumar

ILP is the methodology for execution of multiple instructions per cycle. It is now desirable to modern processors for better performance. It has been observed that ILP is greatly forced by branch instructions. The main idea behind ... celý popis

50.11

Bežne: 52.71 €

Ušetríte 2.60 €


U vydavateľa na objednávku
Odosielame za 3 - 5 dní
Pridať medzi želanie

Mohlo by sa vám tiež páčiť

Darčekový poukaz: Radosť zaručená
  1. Darujte poukaz v ľubovoľnej hodnote, a my sa postaráme o zvyšok.
  2. Poukaz sa vzťahuje na všetky produkty v našej ponuke.
  3. Elektronický poukaz si vytlačíte z e-mailu a môžete ho ihneď darovať.
  4. Platnosť poukazu je 12 mesiacov od dátumu vystavenia.

Objednať darčekový poukazViac informácií

Viac informácií o knihe Instruction Level Parallelism

Nákupom získate 124 bodov

Anotácia knihy

ILP is the methodology for execution of multiple instructions per cycle. It is now desirable to modern processors for better performance. It has been observed that ILP is greatly forced by branch instructions. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the architecture to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision for ILP. The navigation bandwidth of prediction mechanism depends upon the degree of ILP. It can be increased by increasing control flow prediction in procedural languages at compile time. The code generation for parallel register share architecture involves some issues that are not present in sequential code compilation and is inherently complex. To resolve such issues, a consistency contract between the code and the machine can be defined and a compiler is required to preserve the contract during the transformation of code. To achieve high level parallelism at faster clock speed it is necessary to require distribution of processor resource and avoiding primitive that require single cycle global communication.

Parametre knihy

50.11

Obľúbené z iného súdka



Osobný odber Bratislava a 2642 dalších

Copyright ©2008-24 najlacnejsie-knihy.sk Všetky práva vyhradenéSúkromieCookies


Môj účet: Prihlásiť sa
Všetky knihy sveta na jednom mieste. Navyše za skvelé ceny.

Nákupný košík ( prázdny )

Vyzdvihnutie v Zásielkovni
zadarmo nad 59,99 €.

Nachádzate sa: