Mohlo by sa vám tiež páčiť

Viac informácií o knihe Practical Guide for SystemVerilog Assertions

• Parametre knihy
• Anotácia kniha
• Obľúbené z iného súdka

Nákupom získate 373 bodov

Anotácia knihy

SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process. Engineers are used to writing testbenches in verilog that help verify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides the engineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.§

Parametre knihy

Zaradenie knihy Knihy po anglicky Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Celý názov: Practical Guide for SystemVerilog Assertions
• Autor: Meyyappan Ramanathan
• Jazyk: Angličtina
• Väzba: Brožovaná
• Počet strán: 334
• EAN: 9781489992796
• ISBN: 9781489992796
• ID: 09165443
• Nakladateľ: Springer-Verlag New York Inc.
• Hmotnosť: 551 g
• Rozmery: 235 × 155 × 17 mm
• Dátum vydania: 04. December 2014

Obľúbené z iného súdka

---

---

---