Systolic Array Optimizing Compiler / Najlacnejšie knihy
Systolic Array Optimizing Compiler

Kód: 01401113

Systolic Array Optimizing Compiler

Autor Monica S. Lam

This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array bu ... celý popis

102.99

Bežne: 111.62 €

Ušetríte 8.63 €


Skladom u dodávateľa
Odosielame za 10 - 13 dní
Pridať medzi želanie

Mohlo by sa vám tiež páčiť

Darujte túto knihu ešte dnes
  1. Objednajte knihu a vyberte Zaslať ako darček.
  2. Obratom obdržíte darovací poukaz na knihu, ktorý môžete ihneď odovzdať obdarovanému.
  3. Knihu zašleme na adresu obdarovaného, o nič sa nestaráte.

Viac informácií

Viac informácií o knihe Systolic Array Optimizing Compiler

Nákupom získate 249 bodov

Anotácia knihy

This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.

Parametre knihy

Zaradenie knihy Knihy po anglicky Mathematics & science Physics Classical mechanics

102.99

Obľúbené z iného súdka



Osobný odber Bratislava a 12744 dalších

Copyright ©2008-26 najlacnejsie-knihy.sk Všetky práva vyhradenéSúkromieCookies


Môj účet: Prihlásiť sa
Všetky knihy sveta na jednom mieste. Navyše za skvelé ceny.

Nákupný košík ( prázdny )

Vyzdvihnutie v Zásielkovni
zadarmo nad 59,99 €.

Nachádzate sa: