Design of Very High-Frequency Multirate Switched-Capacitor Circuits / Najlacnejšie knihy
Design of Very High-Frequency Multirate Switched-Capacitor Circuits

Kód: 01381376

Design of Very High-Frequency Multirate Switched-Capacitor Circuits

Autor U. Seng-Pan, Rui P. da Silva Martins, José Epifânio da Franca

Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on ... celý popis

138.31


Skladom u dodávateľa v malom množstve
Odosielame za 12 - 15 dní

Potrebujete viac kusov?Ak máte záujem o viac kusov, preverte, prosím, najprv dostupnosť titulu na našej zákazníckej podpore.


Pridať medzi želanie

Mohlo by sa vám tiež páčiť

Darčekový poukaz: Radosť zaručená
  1. Darujte poukaz v ľubovoľnej hodnote, a my sa postaráme o zvyšok.
  2. Poukaz sa vzťahuje na všetky produkty v našej ponuke.
  3. Elektronický poukaz si vytlačíte z e-mailu a môžete ho ihneď darovať.
  4. Platnosť poukazu je 12 mesiacov od dátumu vystavenia.

Objednať darčekový poukazViac informácií

Viac informácií o knihe Design of Very High-Frequency Multirate Switched-Capacitor Circuits

Nákupom získate 345 bodov

Anotácia knihy

Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed:-Optimum circuit architecture tradeoff analysis-Simple speed and power trade-off analysis of active elements-High-order filtering response accuracy with respect to capacitor-ratio mismatches-Time-interleaved effect with respect to gain and offset mismatch-Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding-Stage noise analysis and allocation scheme-Substrate and supply noise reduction-Gain-and offset-compensation techniques-High-bandwidth low-power amplifier design and layout-Very low timing-skew multiphase generationTwo tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.

Parametre knihy

Zaradenie knihy Knihy po anglicky Computing & information technology Computer science

138.31

Obľúbené z iného súdka



Osobný odber Bratislava a 2642 dalších

Copyright ©2008-24 najlacnejsie-knihy.sk Všetky práva vyhradenéSúkromieCookies


Môj účet: Prihlásiť sa
Všetky knihy sveta na jednom mieste. Navyše za skvelé ceny.

Nákupný košík ( prázdny )

Vyzdvihnutie v Zásielkovni
zadarmo nad 59,99 €.

Nachádzate sa: