Kód: 18049815
Using Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design pra ... celý popis
Angličtina
80.70 €
Bežne: 89.41 €
Ušetríte 8.71 €

Nákupom získate 195 bodov
Anotácia knihy
Using Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design practices and methodologies.
Parametre knihy
Zaradenie knihy Knihy po anglicky Technology, engineering, agriculture Electronics & communications engineering Electronics engineering
80.70 €
Angličtina
Osobný odber Bratislava a 12542 dalších
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