Kód: 08142843
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed the location of the fault is known and the ... celý popis
Angličtina
15.69 €
Bežne: 16.06 €
Ušetríte 0.37 €

Nákupom získate 38 bodov
Anotácia knihy
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the JTAG port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicates there is no consistently better replacement method regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is no preferred replacement method that will result in the lowest reconfiguration time.
Parametre knihy
Zaradenie knihy Knihy po anglicky Society & social sciences Education
15.69 €
Angličtina
Osobný odber Bratislava a 12840 dalších
Copyright ©2008-26 najlacnejsie-knihy.sk Všetky práva vyhradenéSúkromieCookies
24 miliónov titulov
Vrátenie do mesiaca
02/210 210 99 (8-15.30h)Nákupný košík ( prázdny )