Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Le / Najlacnejšie knihy
Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Le

Kód: 04334131

Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Le

Autor Colin J. Ihrig

Modern electronic design automation tools can be §used to apply a variety of transformations to §hardware blocks in an effort to achieve performance §and power savings. A number of such transformations §require tools with intimate ... celý popis

49.01

Bežne: 50.03 €

Ušetríte 1.02 €


Skladom u dodávateľa
Odosielame za 9 - 15 dní
Pridať medzi želanie

Mohlo by sa vám tiež páčiť

Darujte túto knihu ešte dnes
  1. Objednajte knihu a vyberte Zaslať ako darček.
  2. Obratom obdržíte darovací poukaz na knihu, ktorý môžete ihneď odovzdať obdarovanému.
  3. Knihu zašleme na adresu obdarovaného, o nič sa nestaráte.

Viac informácií

Viac informácií o knihe Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Le

Nákupom získate 118 bodov

Anotácia knihy

Modern electronic design automation tools can be §used to apply a variety of transformations to §hardware blocks in an effort to achieve performance §and power savings. A number of such transformations §require tools with intimate knowledge of the §design's timing characteristics. Static timing §analysis estimates the worst-case timing behavior of §hardware data flow graphs. The static timing §analyzer described in this book operates on §data flow graphs which are generated as intermediate §representations within a C to VHDL hardware §acceleration compiler. Two additional tools were §then developed which utilize the results of the §static timing analysis. An automated pipelining §tool was developed to increase the throughput of §large blocks of combinational logic generated by the §compiler. Another tool was designed to mitigate §power consumption resulting from combinational §glitching. By inserting special signal buffers with §preselected propagation delays, known as delay §elements, functional units can be kept inactive §until their inputs stabilize. This book explores §these tools as well as the various design tradeoffs §resulting from their use.

Parametre knihy

Zaradenie knihy Knihy po anglicky Computing & information technology Information technology: general issues

49.01

Obľúbené z iného súdka



Osobný odber Bratislava a 12762 dalších

Copyright ©2008-26 najlacnejsie-knihy.sk Všetky práva vyhradenéSúkromieCookies


Môj účet: Prihlásiť sa
Všetky knihy sveta na jednom mieste. Navyše za skvelé ceny.

Nákupný košík ( prázdny )

Vyzdvihnutie v Zásielkovni
zadarmo nad 59,99 €.

Nachádzate sa: