Kód: 07408037
Shows how to develop, document, simulate and synthesize a design using the VHDL language. The text includes a number of paper exercises and computer lab experiments. For practical purposes, the work keeps simulator-specific text t ... celý popis
137.93 €
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Nákupom získate 345 bodov
Shows how to develop, document, simulate and synthesize a design using the VHDL language. The text includes a number of paper exercises and computer lab experiments. For practical purposes, the work keeps simulator-specific text to a minimum.
Zaradenie knihy Knihy po anglicky Technology, engineering, agriculture Electronics & communications engineering Electronics engineering
137.93 €
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