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Anotácia knihy

This book serves as a comprehensive guide, enabling readers to reap the full benefits of assertion-based verification, thereby minimizing hardware verification cost. Detailed descriptions of the SystemVerilog Assertions (SVA) language features are provided throughout the book, along with step-by-step examples of how they can be used to construct powerful sets of property checkers. This second edition includes a description of features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the enhanced assertion constructs of the language, making it usable and accessible for designers, verification engineers, and EDA tool developers.

Parametre knihy

Zaradenie knihy Knihy po anglicky Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Celý názov: SVA: The Power of Assertions in SystemVerilog
• Autor: Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
• Jazyk: Angličtina
• Väzba: Pevná
• Počet strán: 590
• EAN: 9783319071381
• ISBN: 3319071386
• ID: 02667801
• Nakladateľ: Springer International Publishing AG
• Hmotnosť: 1050 g
• Rozmery: 242 × 163 × 38 mm
• Dátum vydania: 24. August 2014

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